In particular because in integrated circuits transistor size continues to decrease under the 100 nm bar by virtue of the advance of technologies such as the CMOS SOI technology, the power consumption associated with static leakage currents is becoming increasingly significant with respect to overall integrated-circuit consumption.
A plurality of techniques, such as power source switching and the use of transistors having a plurality of threshold voltages, commonly referred to as multi-threshold CMOS (MTCMOS) transistors in the art, have been adopted to decrease the consumption associated with static leakage currents.
Nevertheless, these techniques cannot preserve data, for example during an integrated-circuit power-source interruption.
Under these circumstances, synchronous data-retention flip-flop circuits are generally used in order not only to decrease the consumption due to static leakage currents, but also to prevent the loss of stored data.
However, the use of synchronous data-retention flip-flop circuits generally requires many control signals and a non-negligible area of silicon.
There is accordingly a need in the art to provide a low-complexity technical solution employing a small area of silicon to decrease the consumption due to leakage currents from a synchronous data-retention flip-flop circuit.